1. Field of the Invention
The present invention relates to a vertical spin transistor and a method of manufacturing the same.
2. Background Art
Conventionally, increases in speed and improvements of performance of MOSFETs have been realized mainly by reducing the device size. However, in recent years, due to the limit in the lithography technique, various proposals concerning new channel materials and channel structures have been actively made. A representative example is a strain application technique for applying strain to Si crystals in a channel section. Besides, a method of using SiGe crystals or Ge crystals in a channel section of a p-type MOSFET is also reported. It is known that the application of strain is also effective for the SiGe crystals and the Ge crystals.
There is also proposed a method such as forming the strained semiconductor layers on a substrate including a semiconductor substrate, an embedded insulating film, and a semiconductor layer, to reduce junction capacitance. According to this method, a strained Si layer is formed by depositing an Si layer on an SiGe layer of an SGOI (Silicon Germanium on Insulator) substrate, instead of depositing an Si layer on an SiGe substrate. In this case, it is reported that, in forming an n-type MOSFET, a device having a high driving current can be realized by using an SGOI substrate having an SiGe layer with lattice relaxation at a Ge composition ratio of about 20%. On the other hand, in forming a p-type MOSFET, it is effective to form a strained SiGe layer or a strained Ge layer on a GOI (Germanium on Insulator) substrate.
An SGOI structure and a GOI structure can be formed by Ge condensation method. The Ge condensation method makes use of a characteristic that Si atoms selectively combine with O atoms when an SOI (Silicon on Insulator) substrate which has an SiGe crystal layer formed on an Si layer of the SOI substrate by epitaxial growth is thermally oxidized at a high temperature. Consequently, the Si atoms are oxidized while the Si layer and the SiGe layer are mixed. As a result, the SiGe layer is thinned and Ge atoms in the SiGe layer are condensed, so that an SGOI structure having a high Ge concentration is formed. Specifically, for example, by forming an SiGe layer having a Ge composition ratio of 10% and the thickness of 200 nm on an Si layer having the thickness of 50 nm on an SOI substrate by epitaxial growth, and thermally oxidizing the SOI substrate at a temperature of 1200 degrees Celsius, an SiGe layer (an SGOI layer) having a Ge composition ratio of 20% and the thickness of 100 nm is obtained. By further continuing the thermal oxidation, a Ge layer (a GOI layer) having the thickness of 20 nm is obtained. In this case, since a melting point of the SiGe layer falls as the Ge composition ratio rises, it is necessary to lower an oxidation temperature gradually to be lower than the melting point.
Here, the strained semiconductor layers will be considered again. In an n-type MOSFET in which strained Si is used for a channel, improvement of a driving current by several tens % to two times can be expected. On the other hand, concerning a p-type MOSFET in which Ge or strained Ge is used for a channel, improvement of mobility by several times or more is reported. Considering a combination with such a p-type MOSFET, a transistor having a higher driving current is required as the n-type MOSFET.
As another technique for coping with the limit in the lithography technique, there is proposed a vertical transistor that makes it possible to realize a channel structure having a short channel length. JP-A H10-22501 (KOKAI) discloses a vertical MOSFET in which a source layer made of a lattice-relaxed SiGe layer is formed on an Si substrate, a channel layer made of a strained Si layer is formed on the source layer, and a drain layer made of an SiGe layer is formed on the channel layer. According to this structure, since, in the band structure of the source/channel interface, the energy level of the conduction band is higher on the source side, it is possible to lead accelerated electrons into the channel layer. In particular, if the channel length is short, the electrons reach the source layer before the speed of the accelerated electrons falls. Therefore, by reducing the channel length, it is possible to realize a high-speed switching device exceeding the conventional limit, due to a synergistic effect with the strain of the channel layer. Moreover, there is also a proposal such as forming a vertical transistor on an SGOI substrate or a GOI substrate.
Besides these new transistors in which channel materials and channel structures are improved, transistors having new functions are also proposed. An example of the transistors is a spin transistor. In the spin transistor, both of a source section and a drain section are formed of magnetic material, and the ON characteristic of the transistor is changed by coincidence and anticoincidence of spin directions of the source section and the drain section. The spin direction can be changed again and again after the transistor is formed, if the transistor has a spin writing line. Therefore, if a gate array of a large number of transistors is formed of spin transistors, it is possible to rewrite the circuit characteristic after the integrated circuit is manufactured. Consequently, a programmable integrated circuit is realized.
However, there is a problem that it is difficult to manufacture the spin transistor. In particular, difficulty in forming source and drain sections is often a problem. This is because, when the source and drain sections are formed, a process such as forming trenches in a substrate and embedding magnetic material in the trenches is necessary.